This invention relates generally to semiconductor integrated circuit memory arrays, including static (SRAM), dynamic (DRAM), and programmable (Flash or E.sup.2). More particularly the invention relates to memory arrays having a plurality of redundant columns and to the sharing of redundant column programming fuse boxes for replacing defective memory columns.
Present semiconductor integrated circuit memories can store many megabits of data. Typically, each memory comprises a plurality of memory arrays with each array reading or writing perhaps a byte of data (e.g., 8-bits) with a plurality of arrays (e.g., 4) being accessed concurrently to provide a data word (e.g. 32-bits).
Each array has a plurality of addressable columns with an additional number of redundant columns for use in replacing defective columns. Heretofore, each redundant column or fixed group of columns has been programmed with its own dedicated programmable fuse box so that each redundant column (or group of columns) can replace a defective column (or group of columns) by programming that particular fuse box. While the provision of individual fuse boxes for individual redundant columns provides maximum flexibility in using the redundant columns, each fuse box requires as much or more surface area as does the redundant column. Also, each fuse box adds capacitive loading to the address bus which slows the speed of operation. Further, when a fuse box is dedicated to always program a group of redundant columns to replace a group of normal columns, as contrasted to a single column, several redundant columns are effectively wasted when a single normal column is defective. The present invention is directed to reducing surface space required by fuse boxes and reducing the capacitive loading of the column address bus by the fuse boxes.